The present invention relates generally to image forming, computing, or microprocessor-based equipment and is particularly directed to clock generators of the type which exhibit low frequency drift. The invention is specifically disclosed as a Direct Digital Synthesizer circuit that uses a digital accumulator""s MSB or its Carry bit to modulate a feedback clock signal to the phase/frequency detector of a Phase Locked Loop.
Phase locked loop circuits have been used as clock generators in the past so that different output frequencies can be generated from a fixed input frequency, such as a clock signal from a crystal clock oscillator. Certain Phase Locked Loop circuits have also been used in the past to create a Spread Spectrum Clock Generator, which again provides frequencies that are different from the input frequency provided by a crystal oscillator. In U.S. Pat. No. 4,965,533, the phase detector of the Phase Locked Loop outputs a continuous position error value between a maximum positive error and a maximum negative error. This phase detector is an analog phase detector, in which the maximum positive error could be a DC voltage at +V, the maximum negative error could be a DC voltage at xe2x88x92V, and no error would be represented by zero (0) VDC.
Other clock circuits using Phase Locked Loops have also been provided in the past in which an accumulator creates an address to a look-up table in a ROM, and the ROM outputs a sine wave phase address that will drive into a digital-to-analog converter. The output of the digital-to-analog converter will then be a voltage sine wave that is used to drive an analog phase detector of the Phase Locked Loop circuit.
Another prior circuit uses a Direct Digital Synthesizer in the feed-forward path of a Spread Spectrum Clock Generator. Such a circuit is disclosed in U.S. Pat. No. 5,488,627, owned by Lexmark International, Inc. (the Assignee of the present invention).
In certain applications, such as laser printers, a highly accurate clock is used to generate video pulses and to perform pulse width modulation on these pulses. These video pulses can represent pixels, and drive the laser diode of a laser printhead. Since the laser diode produces images on a photoconductive member that is used to deposit toner on a printed page, the pulse placement within a pixel location on a page determines the appearance of the image. Moreover, the video pulse width determines the darkness of this printed image.
The frequency of the pel/slice clock is determined by the scan rate of the laser, which is the speed that the laser beam moves across the photoconductive drum due to the laser beam striking a rotating mirror. Different laser printers, however, scan the laser at different rates. Therefore, different printer designs will typically require a different clock frequency to generate the video signals. Because of this factor, most laser printers contain a unique crystal clock and a standard Phase Locked Loop circuit to produce the video clock signals. Any change in the video clock frequency for a different printer design will require a new crystal (or other type of clock source) to be supplied. This usually takes several weeks, and can delay the start of production of a new design.
Accordingly, it is a primary advantage of the present invention to provide a clock generation circuit that allows the use of a standard input clock frequency to produce an output clock signal that can have a highly selectable output frequency. It is another advantage of the present invention to provide a clock circuit that uses a standard input frequency to create a Spread Spectrum Clock Generator that will operate at different frequency ranges using the same hardware components. It is a further advantage of the present invention to provide a clock circuit with optional frequency multiply or frequency divide circuits that can be used to produce a clock of any frequency for digital logic circuits, even though the input source is a standard fixed clock frequency.
Additional advantages and other novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
To achieve the foregoing and other advantages, and in accordance with one aspect of the present invention, an improved clock generation circuit is provided that operates with a single input clock frequency, and includes a digital Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop in which either the Most Significant Bit or the Carry Bit of the binary adder of the accumulator circuit (which also is known as a numerical oscillator) is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a register with a fixed add/phase amount is used to drive one of the inputs of the binary adder for output circuits that require a fixed output frequency. In addition, a pre-multiply or pre-divide circuit optionally can be provided at the input to either increase or decrease the frequency of the input clock signal before it reaches the phase/frequency detector of the PLL. The output frequency from the voltage controlled oscillator (VCO) also can be optionally divided to provide a lower output clock frequency, if desired. Moreover, the VCO""s output frequency can be divided in the feedback loop before it is directed into the digital accumulator.
The granularity of the output clock frequency and the clock frequency drift are determined by the construction of the circuit. The digital accumulator includes an N-bit adder, and the adder""s output is directed to the input of a set of D flip-flops. These flip-flops are clocked by the output of the VCO clock (or a divided down version of that clock), and the outputs of these D flip-flops are fed back into one of the inputs of the binary adder. A preloaded binary number is also fed into the other input of the adder circuit, and this preloaded number is determined by the desired frequency to be output from the circuit.
The output of the digital accumulator is fed as a modulated feedback clock to the phase/frequency detector of the PLL circuit. This modulated feedback clock preferably is the Most Significant Bit from the accumulator, or alternatively it could be the Carry Bit of the accumulator. In either case, both the MSB and the Carry Bit occur at the same frequency, and will have virtually the same effect on the phase/frequency detector. This will provide equal spacing per count sequence. Furthermore, any specific count decoded from the accumulator, such as comparison, equality, or inequality logic, will also result in the same frequency.
In the configuration where the add/phase register provides a constant number, the output frequency of the circuit will be a constant frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. This can be accomplished by communicating the MSB or Carry Bit to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder. If a periodic modulation is desired, then the address look-up table will point to add amounts that create a particular periodic output frequency profile. This could include a Spread Spectrum profile.
The Add Amount Modulator can be synchronized with an external signal, such as the start signal of a laser scan (e.g., the HSYNC signal). In addition, the Add Amount Modulator can output a synchronization signal so that more than one clock generator can be daisy chained to operate in synchronization with one another.
The Add Amount Modulator can further include a Base Number register that can be added to the numeric values stored in the RAM or ROM memory circuit so as to keep the size of this memory circuit to a reasonably small value. In addition, a Start Number register can be provided in situations where the look-up table is in RAM, and will not be loaded with correct values until after an initialization procedure has been completed. In that situation, the Start Number register can provide values for the modulated add amount that is directed to the binary adder of the accumulator. This also can be used to increase the charge pump current of a programmable charge pump if it is desirable to speed up the process of locking the Phase Locked Loop circuit.
The Add Amount Modulator can be constructed in various configurations, and some of its optional registers can be eliminated under certain circumstances. In addition, the modulation of the frequency profile can be turned off if desired, in situations where certain circuit parameters are to be reset or changed in other ways. An example of this is to change the operating point of a laser printer.
One primary purpose of using the circuit of the present invention is to provide a single hardware design that can be used to generate virtually any frequency for either a constant frequency clock or a modulating frequency clock, all based upon an input clock signal that does not change. The use of optional frequency divide or frequency multiplier circuits allows great flexibility in the input frequencies versus output frequencies of the present invention""s hardware design.
Still other advantages of the present invention will become apparent to those skilled in this art from the following description and drawings wherein there is described and shown a preferred embodiment of this invention in one of the best modes contemplated for carrying out the invention. As will be realized, the invention is capable of other different embodiments, and its several details are capable of modification in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.